One of the difficulties in hardware implementation of some compression algorithms is memory access and reset. In a high data rate system in which output is generated in parallel, it may be a challenge to run the compression algorithm at a high speed or rate in a deterministic way. In previous methods, the input data would be compared to every address location of a memory to determine if the sequence of the input data was previously seen. As a result, performing the dictionary based compression was process intensive and inefficient.